[vm, ffi] Distinguish the Dart names for registers from their standard ABI names.
TEST=ci
Change-Id: I7e3f5b407370aecba49049965071d7409c38177c
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/232481
Reviewed-by: Daco Harkes <dacoharkes@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
diff --git a/runtime/vm/compiler/assembler/assembler_arm64_test.cc b/runtime/vm/compiler/assembler/assembler_arm64_test.cc
index 97ce2ab..4c40284 100644
--- a/runtime/vm/compiler/assembler/assembler_arm64_test.cc
+++ b/runtime/vm/compiler/assembler/assembler_arm64_test.cc
@@ -349,8 +349,8 @@
"movn r2, #0x0\n"
"movz r1, #0x1\n"
"movz r0, #0x0\n"
- "adds ip0, r2, r1\n"
- "adcs ip0, r2, r0\n"
+ "adds tmp, r2, r1\n"
+ "adcs tmp, r2, r0\n"
"adc r0, r0, r0\n"
"ret\n");
}
@@ -370,8 +370,8 @@
EXPECT_DISASSEMBLY(
"movz r1, #0x1\n"
"movz r0, #0x0\n"
- "subs ip0, r0, r1\n"
- "sbcs ip0, r0, r0\n"
+ "subs tmp, r0, r1\n"
+ "sbcs tmp, r0, r0\n"
"sbc r0, r0, r0\n"
"ret\n");
}
@@ -395,8 +395,8 @@
"movz r1, #0x1\n"
"movn r2, #0x0\n"
"mov r3, 0x7fffffffffffffff\n"
- "adds ip0, r2, r1\n"
- "adcs ip0, r3, r0\n"
+ "adds tmp, r2, r1\n"
+ "adcs tmp, r3, r0\n"
"csinc r0, r0, r0, vs\n"
"ret\n");
}
@@ -418,8 +418,8 @@
"movn r2, #0x0\n"
"movz r1, #0x1\n"
"movz r0, #0x0\n"
- "addws ip0, r2, r1\n"
- "adcws ip0, r2, r0\n"
+ "addws tmp, r2, r1\n"
+ "adcws tmp, r2, r0\n"
"adcw r0, r0, r0\n"
"ret\n");
}
@@ -439,8 +439,8 @@
EXPECT_DISASSEMBLY(
"movz r1, #0x1\n"
"movz r0, #0x0\n"
- "subws ip0, r0, r1\n"
- "sbcws ip0, r0, r0\n"
+ "subws tmp, r0, r1\n"
+ "sbcws tmp, r0, r0\n"
"sbcw r0, r0, r0\n"
"ret\n");
}
@@ -464,8 +464,8 @@
"movz r1, #0x1\n"
"mov r2, 0xffffffff\n"
"mov r3, 0x7fffffff\n"
- "addws ip0, r2, r1\n"
- "adcws ip0, r3, r0\n"
+ "addws tmp, r2, r1\n"
+ "adcws tmp, r3, r0\n"
"csinc r0, r0, r0, vs\n"
"ret\n");
}
@@ -489,14 +489,14 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x10\n"
"movz r0, #0x2b\n"
"movz r1, #0x2a\n"
- "str r1, [r15, #-8]!\n"
- "ldr r0, [r15], #8 !\n"
- "mov csp, r15\n"
+ "str r1, [sp, #-8]!\n"
+ "ldr r0, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -515,14 +515,14 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x2b\n"
"movz r1, #0x2a\n"
- "add r2, r15, #0x1\n"
+ "add r2, sp, #0x1\n"
"str r1, [r2, #-1]\n"
"ldr r0, [r2, #-1]\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -548,15 +548,15 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x100\n"
"movz r0, #0x2b\n"
"movz r1, #0x2a\n"
- "str r1, [r15, #-256]!\n"
- "ldr r0, [r15], #248 !\n"
- "add r15, r15, #0x8\n"
- "mov csp, r15\n"
+ "str r1, [sp, #-256]!\n"
+ "ldr r0, [sp], #248 !\n"
+ "add sp, sp, #0x8\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -577,16 +577,16 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x2b\n"
"movz r1, #0x2a\n"
- "sub r15, r15, #0x1000\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "str r1, [r15, #4096]\n"
- "add r15, r15, #0x1000\n"
- "ldr r0, [r15]\n"
- "mov csp, r15\n"
+ "sub sp, sp, #0x1000\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "str r1, [sp, #4096]\n"
+ "add sp, sp, #0x1000\n"
+ "ldr r0, [sp]\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -611,18 +611,18 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x2b\n"
"movz r1, #0x2a\n"
"movz r2, #0xfff8\n"
"movk r2, #0xffff lsl 16\n"
- "str r1, [r15, r2 sxtw]\n"
- "sub r15, r15, #0x8\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "ldr r0, [r15]\n"
- "add r15, r15, #0x8\n"
- "mov csp, r15\n"
+ "str r1, [sp, r2 sxtw]\n"
+ "sub sp, sp, #0x8\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "ldr r0, [sp]\n"
+ "add sp, sp, #0x8\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -645,17 +645,17 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x2b\n"
"movz r1, #0x2a\n"
"movz r2, #0xa\n"
- "sub r15, r15, #0x50\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "str r1, [r15, r2 uxtx scaled]\n"
- "ldr r0, [r15, r2 uxtx scaled]\n"
- "add r15, r15, #0x50\n"
- "mov csp, r15\n"
+ "sub sp, sp, #0x50\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "str r1, [sp, r2 uxtx scaled]\n"
+ "ldr r0, [sp, r2 uxtx scaled]\n"
+ "add sp, sp, #0x50\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -677,14 +677,14 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x10\n"
"mov r1, 0xffffffff\n"
- "strw r1, [r15, #-4]!\n"
- "ldrsw r0, [r15]\n"
- "ldrsw r1, [r15], #4 !\n"
- "mov csp, r15\n"
+ "strw r1, [sp, #-4]!\n"
+ "ldrsw r0, [sp]\n"
+ "ldrsw r1, [sp], #4 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -707,15 +707,15 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x10\n"
"movz r2, #0x2b\n"
"movz r3, #0x2a\n"
- "stp r2, r3, [r15, #-16]!\n"
- "ldp r0, r1, [r15], #16 !\n"
+ "stp r2, r3, [sp, #-16]!\n"
+ "ldp r0, r1, [sp], #16 !\n"
"sub r0, r0, r1\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -737,17 +737,17 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r2, #0x2b\n"
"movz r3, #0x2a\n"
- "sub r15, r15, #0x20\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "stp r2, r3, [r15, #16]\n"
- "ldp r0, r1, [r15, #16]\n"
- "add r15, r15, #0x20\n"
+ "sub sp, sp, #0x20\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "stp r2, r3, [sp, #16]\n"
+ "ldp r0, r1, [sp, #16]\n"
+ "add sp, sp, #0x20\n"
"sub r0, r0, r1\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -767,14 +767,14 @@
typedef int (*PushRegisterPair)() DART_UNUSED;
EXPECT_EQ(12, EXECUTE_TEST_CODE_INT64(PushRegisterPair, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r2, #0xc\n"
"movz r3, #0x15\n"
- "stp r2, r3, [r15, #-16]!\n"
- "ldr r0, [r15], #8 !\n"
- "ldr r1, [r15], #8 !\n"
- "mov csp, r15\n"
+ "stp r2, r3, [sp, #-16]!\n"
+ "ldr r0, [sp], #8 !\n"
+ "ldr r1, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -795,14 +795,14 @@
EXPECT_EQ(12,
EXECUTE_TEST_CODE_INT64(PushRegisterPairReversed, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r3, #0xc\n"
"movz r2, #0x15\n"
- "stp r3, r2, [r15, #-16]!\n"
- "ldr r0, [r15], #8 !\n"
- "ldr r1, [r15], #8 !\n"
- "mov csp, r15\n"
+ "stp r3, r2, [sp, #-16]!\n"
+ "ldr r0, [sp], #8 !\n"
+ "ldr r1, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -822,14 +822,14 @@
typedef int (*PopRegisterPair)() DART_UNUSED;
EXPECT_EQ(12, EXECUTE_TEST_CODE_INT64(PopRegisterPair, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r2, #0xc\n"
"movz r3, #0x15\n"
- "str r3, [r15, #-8]!\n"
- "str r2, [r15, #-8]!\n"
- "ldp r0, r1, [r15], #16 !\n"
- "mov csp, r15\n"
+ "str r3, [sp, #-8]!\n"
+ "str r2, [sp, #-8]!\n"
+ "ldp r0, r1, [sp], #16 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -850,14 +850,14 @@
EXPECT_EQ(12,
EXECUTE_TEST_CODE_INT64(PopRegisterPairReversed, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r3, #0xc\n"
"movz r2, #0x15\n"
- "str r3, [r15, #-8]!\n"
- "str r2, [r15, #-8]!\n"
- "ldp r1, r0, [r15], #16 !\n"
- "mov csp, r15\n"
+ "str r3, [sp, #-8]!\n"
+ "str r2, [sp, #-8]!\n"
+ "ldp r1, r0, [sp], #16 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -882,17 +882,17 @@
typedef intptr_t (*Semaphore)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Semaphore, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x28\n"
"movz r1, #0x2a\n"
- "str r0, [r15, #-8]!\n"
- "ldxr r0, r15\n"
- "stxr ip0, r1, r15\n"
- "cmp ip0, #0x0\n"
+ "str r0, [sp, #-8]!\n"
+ "ldxr r0, sp\n"
+ "stxr tmp, r1, sp\n"
+ "cmp tmp, #0x0\n"
"bne -12\n"
- "ldr r0, [r15], #8 !\n"
- "mov csp, r15\n"
+ "ldr r0, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -915,17 +915,17 @@
typedef intptr_t (*FailedSemaphore)() DART_UNUSED;
EXPECT_EQ(41, EXECUTE_TEST_CODE_INT64(FailedSemaphore, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x28\n"
"movz r1, #0x2a\n"
- "str r0, [r15, #-8]!\n"
- "ldxr r0, r15\n"
+ "str r0, [sp, #-8]!\n"
+ "ldxr r0, sp\n"
"clrex\n"
- "stxr ip0, r1, r15\n"
- "ldr r0, [r15], #8 !\n"
- "add r0, r0, ip0\n"
- "mov csp, r15\n"
+ "stxr tmp, r1, sp\n"
+ "ldr r0, [sp], #8 !\n"
+ "add r0, r0, tmp\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -959,19 +959,19 @@
EXPECT_EQ(42 + (DART_INT64_C(40) << 32),
EXECUTE_TEST_CODE_INT64(Semaphore32, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x28\n"
"add r0, r0, r0 lsl #32\n"
- "str r0, [r15, #-8]!\n"
+ "str r0, [sp, #-8]!\n"
"movz r0, #0x28\n"
"movz r1, #0x2a\n"
- "ldxrw r0, r15\n"
- "stxrw ip0, r1, r15\n"
- "cmp ip0, #0x0\n"
+ "ldxrw r0, sp\n"
+ "stxrw tmp, r1, sp\n"
+ "cmp tmp, #0x0\n"
"bne -12\n"
- "ldr r0, [r15], #8 !\n"
- "mov csp, r15\n"
+ "ldr r0, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -1001,19 +1001,19 @@
EXPECT_EQ(41 + (DART_INT64_C(40) << 32),
EXECUTE_TEST_CODE_INT64(FailedSemaphore32, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"movz r0, #0x28\n"
"add r0, r0, r0 lsl #32\n"
- "str r0, [r15, #-8]!\n"
+ "str r0, [sp, #-8]!\n"
"movz r0, #0x28\n"
"movz r1, #0x2a\n"
- "ldxrw r0, r15\n"
+ "ldxrw r0, sp\n"
"clrex\n"
- "stxrw ip0, r1, r15\n"
- "ldr r0, [r15], #8 !\n"
- "add r0, r0, ip0\n"
- "mov csp, r15\n"
+ "stxrw tmp, r1, sp\n"
+ "ldr r0, [sp], #8 !\n"
+ "add r0, r0, tmp\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -1072,66 +1072,66 @@
EXPECT_EQ(0x42,
EXECUTE_TEST_CODE_INT64(LoadAcquireStoreRelease, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "stp fp, lr, [r15, #-16]!\n"
- "mov fp, r15\n"
- "movz ip0, #0x7788\n"
- "movk ip0, #0x5566 lsl 16\n"
- "movk ip0, #0x3344 lsl 32\n"
- "movk ip0, #0x1122 lsl 48\n"
- "str ip0, [r15, #-8]!\n"
- "ldar r1, r15\n"
- "movz ip1, #0x7788\n"
- "movk ip1, #0x5566 lsl 16\n"
- "movk ip1, #0x3344 lsl 32\n"
- "movk ip1, #0x1122 lsl 48\n"
- "cmp r1, ip1\n"
+ "stp fp, lr, [sp, #-16]!\n"
+ "mov fp, sp\n"
+ "movz tmp, #0x7788\n"
+ "movk tmp, #0x5566 lsl 16\n"
+ "movk tmp, #0x3344 lsl 32\n"
+ "movk tmp, #0x1122 lsl 48\n"
+ "str tmp, [sp, #-8]!\n"
+ "ldar r1, sp\n"
+ "movz tmp2, #0x7788\n"
+ "movk tmp2, #0x5566 lsl 16\n"
+ "movk tmp2, #0x3344 lsl 32\n"
+ "movk tmp2, #0x1122 lsl 48\n"
+ "cmp r1, tmp2\n"
"bne +164\n"
- "add r15, r15, #0x8\n"
- "movz ip0, #0x7788\n"
- "movk ip0, #0x5566 lsl 16\n"
- "movk ip0, #0x3344 lsl 32\n"
- "movk ip0, #0x1122 lsl 48\n"
- "str ip0, [r15, #-8]!\n"
- "ldarw r1, r15\n"
- "movz ip1, #0x7788\n"
- "movk ip1, #0x5566 lsl 16\n"
- "cmp r1, ip1\n"
+ "add sp, sp, #0x8\n"
+ "movz tmp, #0x7788\n"
+ "movk tmp, #0x5566 lsl 16\n"
+ "movk tmp, #0x3344 lsl 32\n"
+ "movk tmp, #0x1122 lsl 48\n"
+ "str tmp, [sp, #-8]!\n"
+ "ldarw r1, sp\n"
+ "movz tmp2, #0x7788\n"
+ "movk tmp2, #0x5566 lsl 16\n"
+ "cmp r1, tmp2\n"
"bne +120\n"
- "add r15, r15, #0x8\n"
- "movz ip0, #0x0\n"
- "str ip0, [r15, #-8]!\n"
+ "add sp, sp, #0x8\n"
+ "movz tmp, #0x0\n"
+ "str tmp, [sp, #-8]!\n"
"movz r1, #0x7788\n"
"movk r1, #0x5566 lsl 16\n"
"movk r1, #0x3344 lsl 32\n"
"movk r1, #0x1122 lsl 48\n"
- "stlr r1, r15\n"
- "ldr r1, [r15], #8 !\n"
- "movz ip1, #0x7788\n"
- "movk ip1, #0x5566 lsl 16\n"
- "movk ip1, #0x3344 lsl 32\n"
- "movk ip1, #0x1122 lsl 48\n"
- "cmp r1, ip1\n"
+ "stlr r1, sp\n"
+ "ldr r1, [sp], #8 !\n"
+ "movz tmp2, #0x7788\n"
+ "movk tmp2, #0x5566 lsl 16\n"
+ "movk tmp2, #0x3344 lsl 32\n"
+ "movk tmp2, #0x1122 lsl 48\n"
+ "cmp r1, tmp2\n"
"bne +60\n"
- "movz ip0, #0x0\n"
- "str ip0, [r15, #-8]!\n"
+ "movz tmp, #0x0\n"
+ "str tmp, [sp, #-8]!\n"
"movz r1, #0x7788\n"
"movk r1, #0x5566 lsl 16\n"
"movk r1, #0x3344 lsl 32\n"
"movk r1, #0x1122 lsl 48\n"
- "stlrw r1, r15\n"
- "ldr r1, [r15], #8 !\n"
- "movz ip1, #0x7788\n"
- "movk ip1, #0x5566 lsl 16\n"
- "cmp r1, ip1\n"
+ "stlrw r1, sp\n"
+ "ldr r1, [sp], #8 !\n"
+ "movz tmp2, #0x7788\n"
+ "movk tmp2, #0x5566 lsl 16\n"
+ "cmp r1, tmp2\n"
"bne +12\n"
"movz r0, #0x42\n"
"b +8\n"
"movz r0, #0x84\n"
- "mov r15, fp\n"
- "ldp fp, lr, [r15], #16 !\n"
- "mov csp, r15\n"
+ "mov sp, fp\n"
+ "ldp fp, lr, [sp], #16 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -1762,12 +1762,12 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "mov ip0, csp\n"
- "sub ip1, csp, #0x1f\n"
- "and csp, ip1, 0xfffffffffffffff0\n"
+ "mov tmp, csp\n"
+ "sub tmp2, csp, #0x1f\n"
+ "and csp, tmp2, 0xfffffffffffffff0\n"
"mov r0, csp\n"
- "sub r0, ip0, r0\n"
- "mov csp, ip0\n"
+ "sub r0, tmp, r0\n"
+ "mov csp, tmp\n"
"ret\n");
}
@@ -2439,18 +2439,18 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v1, ip0\n"
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v2, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v2, tmp\n"
"fcmpd v1, v2\n"
"beq +12\n"
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"ret\n");
}
@@ -2546,18 +2546,18 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x2000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v1, ip0\n"
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v2, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x2000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v2, tmp\n"
"fcmpd v1, v2\n"
"beq +12\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"ret\n");
}
@@ -2598,18 +2598,18 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x6000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v1, ip0\n"
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v2, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x6000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v2, tmp\n"
"fcmpd v1, v2\n"
"blt +12\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"ret\n");
}
@@ -2632,19 +2632,19 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x6000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x2000 lsl 32\n"
- "movk ip0, #0x406d lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x6000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x2000 lsl 32\n"
+ "movk tmp, #0x406d lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcmpd v1, #0.0\n"
"bgt +16\n"
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"ret\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"ret\n");
}
@@ -4276,11 +4276,11 @@
EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()),
0.0001f);
EXPECT_DISASSEMBLY(
- "movz ip0, #0xa19c\n"
- "movk ip0, #0xdc87 lsl 16\n"
- "movk ip0, #0x6c87 lsl 32\n"
- "movk ip0, #0x419d lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0xa19c\n"
+ "movk tmp, #0xdc87 lsl 16\n"
+ "movk tmp, #0x6c87 lsl 32\n"
+ "movk tmp, #0x419d lsl 48\n"
+ "fmovdr v0, tmp\n"
"ret\n");
}
@@ -4372,14 +4372,14 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x10\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
- "fstrd v1, [r15, #-8]!\n"
- "fldrd v0, [r15], #8 !\n"
- "mov csp, r15\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "fstrd v1, [sp, #-8]!\n"
+ "fldrd v0, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -4402,16 +4402,16 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x10\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v2, v1\n"
- "fstrs v2, [r15, #-8]!\n"
- "fldrs v3, [r15], #8 !\n"
+ "fstrs v2, [sp, #-8]!\n"
+ "fldrs v3, [sp], #8 !\n"
"fcvtds v0, v3\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -4441,22 +4441,22 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x10\n"
"fmovd v1, 21.000000\n"
"fmovd v2, 21.000000\n"
"movz r1, #0x2a\n"
- "str r1, [r15, #-8]!\n"
- "fstrd v1, [r15, #-8]!\n"
- "fstrd v2, [r15, #-8]!\n"
- "fldrq v3, [r15], #16 !\n"
- "ldr r0, [r15], #8 !\n"
- "fstrq v3, [r15, #-16]!\n"
- "fldrd v0, [r15], #8 !\n"
- "fldrd v1, [r15], #8 !\n"
+ "str r1, [sp, #-8]!\n"
+ "fstrd v1, [sp, #-8]!\n"
+ "fstrd v2, [sp, #-8]!\n"
+ "fldrq v3, [sp], #16 !\n"
+ "ldr r0, [sp], #8 !\n"
+ "fstrq v3, [sp, #-16]!\n"
+ "fldrd v0, [sp], #8 !\n"
+ "fldrd v1, [sp], #8 !\n"
"faddd v0, v0, v1\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -4470,9 +4470,9 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtzs r0, v0\n"
"ret\n");
}
@@ -4488,9 +4488,9 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0xc045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0xc045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtzsw r0, v0\n"
"sxtw r0, r0\n"
"ret\n");
@@ -4517,11 +4517,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMinInt64, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x8c40\n"
- "movk ip0, #0x78b5 lsl 16\n"
- "movk ip0, #0xaf1d lsl 32\n"
- "movk ip0, #0xc415 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x8c40\n"
+ "movk tmp, #0x78b5 lsl 16\n"
+ "movk tmp, #0xaf1d lsl 32\n"
+ "movk tmp, #0xc415 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtzs r0, v0\n"
"ret\n");
}
@@ -4536,10 +4536,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMaxInt32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x2000 lsl 16\n"
- "movk ip0, #0xa05f lsl 32\n"
- "movk ip0, #0x4202 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x2000 lsl 16\n"
+ "movk tmp, #0xa05f lsl 32\n"
+ "movk tmp, #0x4202 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtzsw r0, v0\n"
"ret\n");
}
@@ -4555,10 +4555,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMinInt32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x2000 lsl 16\n"
- "movk ip0, #0xa05f lsl 32\n"
- "movk ip0, #0xc202 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x2000 lsl 16\n"
+ "movk tmp, #0xa05f lsl 32\n"
+ "movk tmp, #0xc202 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtzsw r0, v0\n"
"sxtw r0, r0\n"
"ret\n");
@@ -4574,9 +4574,9 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(43, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtps r0, v0\n"
"ret\n");
}
@@ -4592,9 +4592,9 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0xc045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0xc045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtpsw r0, v0\n"
"sxtw r0, r0\n"
"ret\n");
@@ -4610,11 +4610,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMaxInt64, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x8c40\n"
- "movk ip0, #0x78b5 lsl 16\n"
- "movk ip0, #0xaf1d lsl 32\n"
- "movk ip0, #0x4415 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x8c40\n"
+ "movk tmp, #0x78b5 lsl 16\n"
+ "movk tmp, #0xaf1d lsl 32\n"
+ "movk tmp, #0x4415 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtps r0, v0\n"
"ret\n");
}
@@ -4629,11 +4629,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMinInt64, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x8c40\n"
- "movk ip0, #0x78b5 lsl 16\n"
- "movk ip0, #0xaf1d lsl 32\n"
- "movk ip0, #0xc415 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x8c40\n"
+ "movk tmp, #0x78b5 lsl 16\n"
+ "movk tmp, #0xaf1d lsl 32\n"
+ "movk tmp, #0xc415 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtps r0, v0\n"
"ret\n");
}
@@ -4648,10 +4648,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMaxInt32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x2000 lsl 16\n"
- "movk ip0, #0xa05f lsl 32\n"
- "movk ip0, #0x4202 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x2000 lsl 16\n"
+ "movk tmp, #0xa05f lsl 32\n"
+ "movk tmp, #0x4202 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtpsw r0, v0\n"
"ret\n");
}
@@ -4667,10 +4667,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMinInt32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x2000 lsl 16\n"
- "movk ip0, #0xa05f lsl 32\n"
- "movk ip0, #0xc202 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x2000 lsl 16\n"
+ "movk tmp, #0xa05f lsl 32\n"
+ "movk tmp, #0xc202 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtpsw r0, v0\n"
"sxtw r0, r0\n"
"ret\n");
@@ -4686,9 +4686,9 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtms r0, v0\n"
"ret\n");
}
@@ -4704,9 +4704,9 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-43, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0xc045 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0xc045 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtmsw r0, v0\n"
"sxtw r0, r0\n"
"ret\n");
@@ -4722,11 +4722,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMaxInt64, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x8c40\n"
- "movk ip0, #0x78b5 lsl 16\n"
- "movk ip0, #0xaf1d lsl 32\n"
- "movk ip0, #0x4415 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x8c40\n"
+ "movk tmp, #0x78b5 lsl 16\n"
+ "movk tmp, #0xaf1d lsl 32\n"
+ "movk tmp, #0x4415 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtms r0, v0\n"
"ret\n");
}
@@ -4741,11 +4741,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMinInt64, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x8c40\n"
- "movk ip0, #0x78b5 lsl 16\n"
- "movk ip0, #0xaf1d lsl 32\n"
- "movk ip0, #0xc415 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x8c40\n"
+ "movk tmp, #0x78b5 lsl 16\n"
+ "movk tmp, #0xaf1d lsl 32\n"
+ "movk tmp, #0xc415 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtms r0, v0\n"
"ret\n");
}
@@ -4760,10 +4760,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMaxInt32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x2000 lsl 16\n"
- "movk ip0, #0xa05f lsl 32\n"
- "movk ip0, #0x4202 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x2000 lsl 16\n"
+ "movk tmp, #0xa05f lsl 32\n"
+ "movk tmp, #0x4202 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtmsw r0, v0\n"
"ret\n");
}
@@ -4779,10 +4779,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(kMinInt32, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x2000 lsl 16\n"
- "movk ip0, #0xa05f lsl 32\n"
- "movk ip0, #0xc202 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x2000 lsl 16\n"
+ "movk tmp, #0xa05f lsl 32\n"
+ "movk tmp, #0xc202 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtmsw r0, v0\n"
"sxtw r0, r0\n"
"ret\n");
@@ -4831,8 +4831,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fabsd v0, v1\n"
"ret\n");
}
@@ -4847,8 +4847,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0xc045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0xc045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fabsd v0, v1\n"
"ret\n");
}
@@ -4863,8 +4863,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(-42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fnegd v0, v1\n"
"ret\n");
}
@@ -4879,8 +4879,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0xc045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0xc045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fnegd v0, v1\n"
"ret\n");
}
@@ -4895,8 +4895,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(8.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4050 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4050 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fsqrtd v0, v1\n"
"ret\n");
}
@@ -4912,8 +4912,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4055 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4055 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fmovd v2, 0.500000\n"
"fmuld v0, v1, v2\n"
"ret\n");
@@ -4930,8 +4930,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4055 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4055 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fmovd v2, 2.000000\n"
"fdivd v0, v1, v2\n"
"ret\n");
@@ -4948,9 +4948,9 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0xc000 lsl 32\n"
- "movk ip0, #0x4044 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0xc000 lsl 32\n"
+ "movk tmp, #0x4044 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fmovd v2, 0.500000\n"
"faddd v0, v1, v2\n"
"ret\n");
@@ -4967,9 +4967,9 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fmovd v2, 0.500000\n"
"fsubd v0, v1, v2\n"
"ret\n");
@@ -4992,19 +4992,19 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
- "sub r15, r15, #0x8\n"
- "add r2, r15, #0x1\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "sub sp, sp, #0x8\n"
+ "add r2, sp, #0x1\n"
"fstrd v1, [r2, #-1]\n"
"fldrd v0, [r2, #-1]\n"
- "add r15, r15, #0x8\n"
- "mov csp, r15\n"
+ "add sp, sp, #0x8\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5030,18 +5030,18 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"sub csp, csp, #0x100\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
- "fstrd v1, [r15, #-256]!\n"
- "fldrd v0, [r15], #248 !\n"
- "add r15, r15, #0x8\n"
- "mov csp, r15\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "fstrd v1, [sp, #-256]!\n"
+ "fldrd v0, [sp], #248 !\n"
+ "add sp, sp, #0x8\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5062,19 +5062,19 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
- "sub r15, r15, #0x1000\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "fstrd v1, [r15, #4096]\n"
- "add r15, r15, #0x1000\n"
- "fldrd v0, [r15]\n"
- "mov csp, r15\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "sub sp, sp, #0x1000\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "fstrd v1, [sp, #4096]\n"
+ "add sp, sp, #0x1000\n"
+ "fldrd v0, [sp]\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5099,21 +5099,21 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"movz r2, #0xfff8\n"
"movk r2, #0xffff lsl 16\n"
- "fstrd v1, [r15, r2 sxtw]\n"
- "sub r15, r15, #0x8\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "fldrd v0, [r15]\n"
- "add r15, r15, #0x8\n"
- "mov csp, r15\n"
+ "fstrd v1, [sp, r2 sxtw]\n"
+ "sub sp, sp, #0x8\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "fldrd v0, [sp]\n"
+ "add sp, sp, #0x8\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5136,20 +5136,20 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"movz r2, #0xa\n"
- "sub r15, r15, #0x50\n"
- "and csp, r15, 0xfffffffffffffff0\n"
- "fstrd v1, [r15, r2 uxtx scaled]\n"
- "fldrd v0, [r15, r2 uxtx scaled]\n"
- "add r15, r15, #0x50\n"
- "mov csp, r15\n"
+ "sub sp, sp, #0x50\n"
+ "and csp, sp, 0xfffffffffffffff0\n"
+ "fstrd v1, [sp, r2 uxtx scaled]\n"
+ "fldrd v0, [sp, r2 uxtx scaled]\n"
+ "add sp, sp, #0x50\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5369,10 +5369,10 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
- "movz ip0, #0xc055 lsl 48\n"
- "fmovdr v2, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "movz tmp, #0xc055 lsl 48\n"
+ "fmovdr v2, tmp\n"
"fcvtsd v1, v1\n"
"fcvtsd v2, v2\n"
"veor v3, v3, v3\n"
@@ -5408,10 +5408,10 @@
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
- "movz ip0, #0xc055 lsl 48\n"
- "fmovdr v2, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
+ "movz tmp, #0xc055 lsl 48\n"
+ "fmovdr v2, tmp\n"
"vinsd v3[0], v1[0]\n"
"vinsd v3[1], v2[0]\n"
"vnegd v4, v3\n"
@@ -5459,8 +5459,8 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(12.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"fmovd v1, 1.000000\n"
"fmovd v2, 2.000000\n"
"fmovd v3, 3.000000\n"
@@ -5527,13 +5527,13 @@
EXPECT_EQ(-6.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"fmovd v1, 1.000000\n"
"fmovd v2, 2.000000\n"
"fmovd v3, 3.000000\n"
- "movz ip0, #0x0\n"
- "fmovdr v5, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v5, tmp\n"
"fcvtsd v0, v0\n"
"fcvtsd v1, v1\n"
"fcvtsd v2, v2\n"
@@ -5596,8 +5596,8 @@
EXPECT_EQ(14.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"fmovd v1, 1.000000\n"
"fmovd v2, 2.000000\n"
"fmovd v3, 3.000000\n"
@@ -5663,8 +5663,8 @@
EXPECT_EQ(4.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"fmovd v1, 1.000000\n"
"fmovd v2, 2.000000\n"
"fmovd v3, 3.000000\n"
@@ -5746,8 +5746,8 @@
EXPECT_DISASSEMBLY(
"fmovd v0, 2.000000\n"
"fmovd v1, 3.000000\n"
- "movz ip0, #0x0\n"
- "fmovdr v5, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v5, tmp\n"
"vinsd v4[0], v0[0]\n"
"vinsd v4[1], v1[0]\n"
"vsubd v5, v5, v4\n"
@@ -5845,16 +5845,16 @@
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"fmovd v0, 21.000000\n"
"vdupd v1, v0[0]\n"
"sub csp, csp, #0x10\n"
- "fstrq v1, [r15, #-16]!\n"
- "fldrd v2, [r15], #8 !\n"
- "fldrd v3, [r15], #8 !\n"
+ "fstrq v1, [sp, #-16]!\n"
+ "fldrd v2, [sp], #8 !\n"
+ "fldrd v3, [sp], #8 !\n"
"faddd v0, v2, v3\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5893,17 +5893,17 @@
EXPECT_EQ(84.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"fmovd v0, 21.000000\n"
"fcvtsd v0, v0\n"
"vdups v1, v0[0]\n"
"sub csp, csp, #0x10\n"
- "fstrq v1, [r15, #-16]!\n"
- "fldrs v3, [r15], #4 !\n"
- "fldrs v2, [r15], #4 !\n"
- "fldrs v1, [r15], #4 !\n"
- "fldrs v0, [r15], #4 !\n"
+ "fstrq v1, [sp, #-16]!\n"
+ "fldrs v3, [sp], #4 !\n"
+ "fldrs v2, [sp], #4 !\n"
+ "fldrs v1, [sp], #4 !\n"
+ "fldrs v0, [sp], #4 !\n"
"fcvtds v0, v0\n"
"fcvtds v1, v1\n"
"fcvtds v2, v2\n"
@@ -5911,7 +5911,7 @@
"faddd v0, v1, v1\n"
"faddd v0, v0, v2\n"
"faddd v0, v0, v3\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5940,17 +5940,17 @@
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
""
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v5, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v5, tmp\n"
"vinsd v1[1], v5[0]\n"
"sub csp, csp, #0x10\n"
- "fstrq v1, [r15, #-16]!\n"
- "fldrd v2, [r15], #8 !\n"
- "fldrd v3, [r15], #8 !\n"
+ "fstrq v1, [sp, #-16]!\n"
+ "fldrd v2, [sp], #8 !\n"
+ "fldrd v3, [sp], #8 !\n"
"fmovdd v0, v3\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -5996,23 +5996,23 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
"fmovd v0, 21.000000\n"
"fcvtsd v0, v0\n"
"vinss v1[3], v0[0]\n"
"vinss v1[1], v0[0]\n"
- "movz ip0, #0x0\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x0\n"
+ "fmovdr v0, tmp\n"
"fcvtsd v0, v0\n"
"vinss v1[2], v0[0]\n"
"vinss v1[0], v0[0]\n"
"sub csp, csp, #0x10\n"
- "fstrq v1, [r15, #-16]!\n"
- "fldrs v3, [r15], #4 !\n"
- "fldrs v2, [r15], #4 !\n"
- "fldrs v1, [r15], #4 !\n"
- "fldrs v0, [r15], #4 !\n"
+ "fstrq v1, [sp, #-16]!\n"
+ "fldrs v3, [sp], #4 !\n"
+ "fldrs v2, [sp], #4 !\n"
+ "fldrs v1, [sp], #4 !\n"
+ "fldrs v0, [sp], #4 !\n"
"fcvtds v0, v0\n"
"fcvtds v1, v1\n"
"fcvtds v2, v2\n"
@@ -6020,7 +6020,7 @@
"faddd v0, v0, v1\n"
"faddd v0, v0, v2\n"
"faddd v0, v0, v3\n"
- "mov csp, r15\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -6350,10 +6350,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(0xfffffffe, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0xc045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0xc045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v0, v0\n"
"fcvtsd v1, v1\n"
"vdups v2, v0[0]\n"
@@ -6393,10 +6393,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0xc045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0xc045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"vdupd v2, v0[0]\n"
"vinsd v3[0], v0[0]\n"
"vinsd v3[1], v1[0]\n"
@@ -6437,10 +6437,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(0xfffffffe, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0xc045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0xc045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v0, v0\n"
"fcvtsd v1, v1\n"
"vdups v2, v0[0]\n"
@@ -6480,10 +6480,10 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0xc045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0xc045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"vdupd v2, v0[0]\n"
"vinsd v3[0], v0[0]\n"
"vinsd v3[1], v1[0]\n"
@@ -6524,11 +6524,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(0xfffffffe, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v0, v0\n"
"fcvtsd v1, v1\n"
"vdups v2, v0[0]\n"
@@ -6568,11 +6568,11 @@
typedef int64_t (*Int64Return)() DART_UNUSED;
EXPECT_EQ(-1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4045 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4045 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4045 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4045 lsl 48\n"
+ "fmovdr v1, tmp\n"
"vdupd v2, v0[0]\n"
"vinsd v3[0], v0[0]\n"
"vinsd v3[1], v1[0]\n"
@@ -6664,9 +6664,9 @@
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
"fmovd v0, 21.000000\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4034 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4034 lsl 48\n"
+ "fmovdr v1, tmp\n"
"vdupd v2, v0[0]\n"
"vinsd v3[0], v0[0]\n"
"vinsd v3[1], v1[0]\n"
@@ -6758,9 +6758,9 @@
EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
"fmovd v0, 21.000000\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4035 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4035 lsl 48\n"
+ "fmovdr v1, tmp\n"
"vdupd v2, v0[0]\n"
"vinsd v3[0], v0[0]\n"
"vinsd v3[1], v1[0]\n"
@@ -6798,11 +6798,11 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(15.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4050 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4048 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4050 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4048 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v0, v0\n"
"fcvtsd v1, v1\n"
"veor v3, v3, v3\n"
@@ -6837,11 +6837,11 @@
typedef double (*DoubleReturn)() DART_UNUSED;
EXPECT_EQ(15.0, EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry()));
EXPECT_DISASSEMBLY(
- "movz ip0, #0x4050 lsl 48\n"
- "fmovdr v0, ip0\n"
- "movz ip0, #0x8000 lsl 32\n"
- "movk ip0, #0x4048 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x4050 lsl 48\n"
+ "fmovdr v0, tmp\n"
+ "movz tmp, #0x8000 lsl 32\n"
+ "movk tmp, #0x4048 lsl 48\n"
+ "fmovdr v1, tmp\n"
"vinsd v3[0], v0[0]\n"
"vinsd v3[1], v1[0]\n"
"vsqrtd v4, v3\n"
@@ -6906,9 +6906,9 @@
float res = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
EXPECT_FLOAT_EQ(arm_recip_estimate(147.0), res, 0.0001);
EXPECT_DISASSEMBLY(
- "movz ip0, #0x6000 lsl 32\n"
- "movk ip0, #0x4062 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x6000 lsl 32\n"
+ "movk tmp, #0x4062 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v1, v1\n"
"vinss v2[0], v1[0]\n"
"vinss v2[1], v1[0]\n"
@@ -6976,11 +6976,11 @@
double res = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
EXPECT_FLOAT_EQ(42.0, res, 0.0001);
EXPECT_DISASSEMBLY(
- "movz ip0, #0x8618\n"
- "movk ip0, #0x1861 lsl 16\n"
- "movk ip0, #0x6186 lsl 32\n"
- "movk ip0, #0x3fb8 lsl 48\n"
- "fmovdr v0, ip0\n"
+ "movz tmp, #0x8618\n"
+ "movk tmp, #0x1861 lsl 16\n"
+ "movk tmp, #0x6186 lsl 32\n"
+ "movk tmp, #0x3fb8 lsl 48\n"
+ "fmovdr v0, tmp\n"
"fcvtsd v0, v0\n"
"vdups v1, v0[0]\n"
"vrecpes v2, v1\n"
@@ -7072,9 +7072,9 @@
double res = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
EXPECT_FLOAT_EQ(arm_reciprocal_sqrt_estimate(147.0), res, 0.0001);
EXPECT_DISASSEMBLY(
- "movz ip0, #0x6000 lsl 32\n"
- "movk ip0, #0x4062 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0x6000 lsl 32\n"
+ "movk tmp, #0x4062 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v1, v1\n"
"vrsqrtes v0, v1\n"
"fcvtds v0, v0\n"
@@ -7125,9 +7125,9 @@
double res = EXECUTE_TEST_CODE_DOUBLE(DoubleReturn, test->entry());
EXPECT_FLOAT_EQ(1.0 / sqrt(147000.0), res, 0.0001);
EXPECT_DISASSEMBLY(
- "movz ip0, #0xf1c0 lsl 32\n"
- "movk ip0, #0x4101 lsl 48\n"
- "fmovdr v1, ip0\n"
+ "movz tmp, #0xf1c0 lsl 32\n"
+ "movk tmp, #0x4101 lsl 48\n"
+ "fmovdr v1, tmp\n"
"fcvtsd v1, v1\n"
"vrsqrtes v0, v1\n"
"vmuls v31, v0, v0\n"
@@ -7318,18 +7318,18 @@
EXPECT_EQ(123, EXECUTE_TEST_CODE_INTPTR_INTPTR(StoreReleaseLoadAcquire,
test->entry(), 123));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "str r1, [r15, #-8]!\n"
+ "str r1, [sp, #-8]!\n"
"movz r1, #0x0\n"
- "str r1, [r15, #-8]!\n"
+ "str r1, [sp, #-8]!\n"
"mov r1, r0\n"
"movz r0, #0x0\n"
- "stlr r1, r15\n"
- "ldar r0, r15\n"
- "ldr r1, [r15], #8 !\n"
- "ldr r1, [r15], #8 !\n"
- "mov csp, r15\n"
+ "stlr r1, sp\n"
+ "ldar r0, sp\n"
+ "ldr r1, [sp], #8 !\n"
+ "ldr r1, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
@@ -7355,22 +7355,22 @@
EXPECT_EQ(123, EXECUTE_TEST_CODE_INTPTR_INTPTR(StoreReleaseLoadAcquire1024,
test->entry(), 123));
EXPECT_DISASSEMBLY(
- "mov r15, csp\n"
+ "mov sp, csp\n"
"sub csp, csp, #0x1000\n"
- "str r1, [r15, #-8]!\n"
+ "str r1, [sp, #-8]!\n"
"movz r1, #0x0\n"
- "str r1, [r15, #-8]!\n"
+ "str r1, [sp, #-8]!\n"
"mov r1, r0\n"
"movz r0, #0x0\n"
- "sub r15, r15, #0x2000\n"
- "add ip0, r15, #0x400\n"
- "stlr r1, ip0\n"
- "add ip1, r15, #0x400\n"
- "ldar r0, ip1\n"
- "add r15, r15, #0x2000\n"
- "ldr r1, [r15], #8 !\n"
- "ldr r1, [r15], #8 !\n"
- "mov csp, r15\n"
+ "sub sp, sp, #0x2000\n"
+ "add tmp, sp, #0x400\n"
+ "stlr r1, tmp\n"
+ "add tmp2, sp, #0x400\n"
+ "ldar r0, tmp2\n"
+ "add sp, sp, #0x2000\n"
+ "ldr r1, [sp], #8 !\n"
+ "ldr r1, [sp], #8 !\n"
+ "mov csp, sp\n"
"ret\n");
}
#endif
diff --git a/runtime/vm/compiler/assembler/assembler_x64_test.cc b/runtime/vm/compiler/assembler/assembler_x64_test.cc
index 761a858..c0acbff 100644
--- a/runtime/vm/compiler/assembler/assembler_x64_test.cc
+++ b/runtime/vm/compiler/assembler/assembler_x64_test.cc
@@ -510,8 +510,8 @@
EXPECT_EQ(1, reinterpret_cast<CmpbCode>(test->entry())());
EXPECT_DISASSEMBLY(
"movl rax,1\n"
- "movl r11,0xffffff11\n"
- "push r11\n"
+ "movl tmp,0xffffff11\n"
+ "push tmp\n"
"cmpb [rsp],0x11\n"
"jz +7\n"
"movl rax,0\n"
@@ -542,8 +542,8 @@
EXPECT_DISASSEMBLY(
"movl rax,1\n"
"movl rcx,0\n"
- "movl r11,0xffffff11\n"
- "push r11\n"
+ "movl tmp,0xffffff11\n"
+ "push tmp\n"
"testb [rsp],0x10\n"
"cmovzq rax,rcx\n"
"testb [rsp],0x20\n"
@@ -951,8 +951,8 @@
__ addq(RAX, R8);
__ movq(R10, Immediate(2));
- __ movq(R11, Immediate(4));
- __ imulq(R10, R11);
+ __ movq(TMP, Immediate(4));
+ __ imulq(R10, TMP);
__ addq(RAX, R10);
__ movq(R15, Immediate(2));
@@ -977,8 +977,8 @@
"pop r9\n"
"addq rax,r8\n"
"movl r10,2\n"
- "movl r11,4\n"
- "imulq r10,r11\n"
+ "movl tmp,4\n"
+ "imulq r10,tmp\n"
"addq rax,r10\n"
"movl pp,2\n"
"imulq pp,pp,4\n"
@@ -1012,8 +1012,8 @@
"movq rax,0x1234567887654321\n"
"movq rcx,0x0db4da5f7ef412b1\n"
"imulq rax,rcx\n"
- "movq r11,0x1234567887654321\n"
- "imulq rcx,r11\n"
+ "movq tmp,0x1234567887654321\n"
+ "imulq rcx,tmp\n"
"cmpq rax,rcx\n"
"jz +7\n"
"int3\n"
@@ -1327,8 +1327,8 @@
typedef intptr_t (*MoveExtend)();
EXPECT_EQ(0x7ffffffe, reinterpret_cast<MoveExtend>(test->entry())());
EXPECT_DISASSEMBLY(
- "movl r11,0xffffffff\n"
- "push r11\n"
+ "movl tmp,0xffffffff\n"
+ "push tmp\n"
"push 0x7fffffff\n"
"movsxdq rdx,[rsp+0x8]\n"
"movsxdq rax,[rsp]\n"
@@ -1770,10 +1770,10 @@
"addq r10,[rsp+0x10]\n"
"movq rax,[rsp+0x8]\n"
"adcq rax,[rsp+0x18]\n"
- "pop r11\n"
- "pop r11\n"
- "pop r11\n"
- "pop r11\n"
+ "pop tmp\n"
+ "pop tmp\n"
+ "pop tmp\n"
+ "pop tmp\n"
"ret\n");
}
@@ -1866,10 +1866,10 @@
"subq r10,[rsp+0x10]\n"
"movq rax,[rsp+0x8]\n"
"sbbq rax,[rsp+0x18]\n"
- "pop r11\n"
- "pop r11\n"
- "pop r11\n"
- "pop r11\n"
+ "pop tmp\n"
+ "pop tmp\n"
+ "pop tmp\n"
+ "pop tmp\n"
"ret\n");
}
@@ -2391,8 +2391,8 @@
"movl rcx,2\n"
"shlq rdx,cl\n"
"shldq rdx,r8,2\n"
- "movq r11,0xf000000000000003\n"
- "cmpq rdx,r11\n"
+ "movq tmp,0xf000000000000003\n"
+ "cmpq rdx,tmp\n"
"jz +7\n"
"int3\n"
"movq rdx,0xff00000000000000\n"
@@ -2400,8 +2400,8 @@
"movl rcx,2\n"
"shlq rdx,cl\n"
"shldq rdx,r8,cl\n"
- "movq r11,0xf000000000000003\n"
- "cmpq rdx,r11\n"
+ "movq tmp,0xf000000000000003\n"
+ "cmpq rdx,tmp\n"
"jz +7\n"
"int3\n"
"movq rdx,0xff00000000000000\n"
@@ -2409,8 +2409,8 @@
"movl rcx,2\n"
"shrq rdx,cl\n"
"shrdq rdx,r8,cl\n"
- "movq r11,0xcff0000000000000\n"
- "cmpq rdx,r11\n"
+ "movq tmp,0xcff0000000000000\n"
+ "cmpq rdx,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0\n"
@@ -2697,31 +2697,31 @@
"movl rax,1\n"
"shlq rax,63\n"
"sarq rax,3\n"
- "movq r11,0xf000000000000000\n"
- "cmpq rax,r11\n"
+ "movq tmp,0xf000000000000000\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,1\n"
"movl rcx,3\n"
"shlq rax,63\n"
"sarq rax,cl\n"
- "movq r11,0xf000000000000000\n"
- "cmpq rax,r11\n"
+ "movq tmp,0xf000000000000000\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"push pp\n"
"movq pp,0xf000000000000001\n"
"andq pp,-1\n"
- "movq r11,0x8000000000000001\n"
- "andq pp,r11\n"
+ "movq tmp,0x8000000000000001\n"
+ "andq pp,tmp\n"
"orq pp,2\n"
- "movq r11,0xf800000000000000\n"
- "orq pp,r11\n"
+ "movq tmp,0xf800000000000000\n"
+ "orq pp,tmp\n"
"xorq pp,1\n"
- "movq r11,0x0800000000000000\n"
- "xorq pp,r11\n"
- "movq r11,0xf000000000000002\n"
- "cmpq pp,r11\n"
+ "movq tmp,0x0800000000000000\n"
+ "xorq pp,tmp\n"
+ "movq tmp,0xf000000000000002\n"
+ "cmpq pp,tmp\n"
"jz +7\n"
"int3\n"
"andl pp,2\n"
@@ -3080,7 +3080,7 @@
typedef int (*CallSimpleLeafCode)();
EXPECT_EQ(42 + 87, reinterpret_cast<CallSimpleLeafCode>(test->entry())());
EXPECT_DISASSEMBLY_ENDS_WITH(
- "call r11\n"
+ "call tmp\n"
"addq rsp,8\n"
"ret\n");
}
@@ -3100,7 +3100,7 @@
ASSEMBLER_TEST_RUN(JumpSimpleLeaf, test) {
typedef int (*JumpSimpleLeafCode)();
EXPECT_EQ(42, reinterpret_cast<JumpSimpleLeafCode>(test->entry())());
- EXPECT_DISASSEMBLY_ENDS_WITH("jmp r11\n");
+ EXPECT_DISASSEMBLY_ENDS_WITH("jmp tmp\n");
}
ASSEMBLER_TEST_GENERATE(JumpIndirect, assembler) {
@@ -3185,7 +3185,7 @@
"movss r8,xmm7\n"
"movss r9,xmm8\n"
"movss r10,xmm9\n"
- "movss r11,xmm10\n"
+ "movss tmp,xmm10\n"
"movss r12,xmm11\n"
"movss r13,xmm12\n"
"movss thr,xmm13\n"
@@ -3209,7 +3209,7 @@
"movss thr,xmm15\n"
"movss r13,xmm14\n"
"movss r12,xmm13\n"
- "movss r11,xmm12\n"
+ "movss tmp,xmm12\n"
"movss r10,xmm11\n"
"movss r9,xmm10\n"
"movss r8,xmm9\n"
@@ -3384,8 +3384,8 @@
EXPECT_FLOAT_EQ(-1.0, res, 0.000001f);
EXPECT_DISASSEMBLY_NOT_WINDOWS_ENDS_WITH(
"movups xmm10,[rax]\n"
- "movq r11,[thr+0x...]\n"
- "xorpd xmm10,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "xorpd xmm10,[tmp]\n"
"movaps xmm0,xmm10\n"
"pop thr\n"
"pop pp\n"
@@ -3413,8 +3413,8 @@
EXPECT_FLOAT_EQ(1.0, res, 0.000001f);
EXPECT_DISASSEMBLY_NOT_WINDOWS_ENDS_WITH(
"movups xmm10,[rax]\n"
- "movq r11,[thr+0x...]\n"
- "movups xmm0,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "movups xmm0,[tmp]\n"
"andpd xmm0,xmm10\n"
"pop thr\n"
"pop pp\n"
@@ -4066,8 +4066,8 @@
"movl rax,0x4144cccd\n"
"movd xmm0,rax\n"
"shufps xmm0,xmm0 [0]\n"
- "movq r11,[thr+0x...]\n"
- "xorps xmm0,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "xorps xmm0,[tmp]\n"
"shufps xmm0,xmm0 [aa]\n"
"pop thr\n"
"pop pp\n"
@@ -4103,8 +4103,8 @@
"movl rax,-0x3e8b3333\n"
"movd xmm0,rax\n"
"shufps xmm0,xmm0 [0]\n"
- "movq r11,[thr+0x...]\n"
- "andps xmm0,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "andps xmm0,[tmp]\n"
"shufps xmm0,xmm0 [aa]\n"
"pop thr\n"
"pop pp\n"
@@ -4138,8 +4138,8 @@
"movl rax,0x4144cccd\n"
"movd xmm0,rax\n"
"shufps xmm0,xmm0 [0]\n"
- "movq r11,[thr+0x...]\n"
- "andps xmm0,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "andps xmm0,[tmp]\n"
"shufps xmm0,xmm0 [ff]\n"
"pop thr\n"
"pop pp\n"
@@ -4288,8 +4288,8 @@
EXPECT_EQ(static_cast<uword>(0x0), res);
EXPECT_DISASSEMBLY_NOT_WINDOWS_ENDS_WITH(
"movups xmm9,[rax]\n"
- "movq r11,[thr+0x...]\n"
- "movups xmm0,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "movups xmm0,[tmp]\n"
"xorps xmm0,xmm9\n"
"push rax\n"
"movss [rsp],xmm0\n"
@@ -4756,10 +4756,10 @@
double res = reinterpret_cast<Int32ToDoubleConversion>(test->entry())();
EXPECT_FLOAT_EQ(-2.0, res, 0.001);
EXPECT_DISASSEMBLY(
- "movq r11,0x1111111100000006\n"
- "cvtsi2sd xmm0,r11\n"
- "movq r11,0x2222222200000008\n"
- "cvtsi2sd xmm8,r11\n"
+ "movq tmp,0x1111111100000006\n"
+ "cvtsi2sd xmm0,tmp\n"
+ "movq tmp,0x2222222200000008\n"
+ "cvtsi2sd xmm8,tmp\n"
"subsd xmm0,xmm8\n"
"ret\n");
}
@@ -4823,8 +4823,8 @@
"movsd xmm9,[rsp]\n"
"pop rax\n"
"cvttsd2siq rax,xmm9\n"
- "movq r11,0x8000000000000000\n"
- "cmpq rax,r11\n"
+ "movq tmp,0x8000000000000000\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movq rax,0x4258727cda000000\n"
@@ -4904,8 +4904,8 @@
"movsd xmm9,[rsp]\n"
"pop rax\n"
"cvttsd2sil rax,xmm9\n"
- "movl r11,0x80000000\n"
- "cmpq rax,r11\n"
+ "movl tmp,0x80000000\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movq rax,0xc045000000000000\n"
@@ -4914,8 +4914,8 @@
"pop rax\n"
"movq r10,-1\n"
"cvttsd2sil r10,xmm9\n"
- "movl r11,0xffffffd6\n"
- "cmpq r10,r11\n"
+ "movl tmp,0xffffffd6\n"
+ "cmpq r10,tmp\n"
"jz +7\n"
"int3\n"
"movq rax,0x4045000000000000\n"
@@ -4991,8 +4991,8 @@
"cmpq rcx,0x1e\n"
"jnz +63\n"
"push rax\n"
- "movq r11,[pp+0xf]\n"
- "movq [rsp],r11\n"
+ "movq tmp,[pp+0xf]\n"
+ "movq [rsp],tmp\n"
"pop rcx\n"
"cmpq rcx,[pp+0xf]\n"
"jnz +43\n"
@@ -5035,8 +5035,8 @@
"cmpl rcx,0x1e\n"
"jnz +62\n"
"push rax\n"
- "movq r11,[pp+0xf]\n"
- "movq [rsp],r11\n"
+ "movq tmp,[pp+0xf]\n"
+ "movq [rsp],tmp\n"
"pop rcx\n"
"cmpl rcx,[pp+0xf]\n"
"jnz +42\n"
@@ -5464,8 +5464,8 @@
"movq r12,[rdi+0x8]\n"
"movq thr,rsi\n"
"movq pp,[r12+0x27]\n"
- "movq r11,[thr+0x...]\n"
- "andpd xmm0,[r11]\n"
+ "movq tmp,[thr+0x...]\n"
+ "andpd xmm0,[tmp]\n"
"pop thr\n"
"pop pp\n"
"pop r12\n"
@@ -5832,8 +5832,8 @@
EXPECT_EQ(1, reinterpret_cast<BitTest>(test->entry())());
EXPECT_DISASSEMBLY(
"movl rax,4\n"
- "movl r11,2\n"
- "btq rax,r11\n"
+ "movl tmp,2\n"
+ "btq rax,tmp\n"
"jc +7\n"
"int3\n"
"movl rax,1\n"
@@ -5855,8 +5855,8 @@
typedef int (*BitTestImmediate)();
EXPECT_EQ(1, reinterpret_cast<BitTestImmediate>(test->entry())());
EXPECT_DISASSEMBLY(
- "movl r11,0x20\n"
- "bt r11,5\n"
+ "movl tmp,0x20\n"
+ "bt tmp,5\n"
"jc +7\n"
"int3\n"
"movl rax,1\n"
@@ -6007,44 +6007,44 @@
EXPECT_DISASSEMBLY(
"movl rax,0x2a\n"
"imulq rax,rax,0x3b9aca00\n"
- "movq r11,0x00000009c7652400\n"
- "cmpq rax,r11\n"
+ "movq tmp,0x00000009c7652400\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x2a\n"
"imull rax,rax,0x3b9aca00\n"
- "movl r11,0xc7652400\n"
- "cmpq rax,r11\n"
+ "movl tmp,0xc7652400\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x3b9aca00\n"
- "movq r11,0x000000098bca5a00\n"
- "addq rax,r11\n"
- "movq r11,0x00000009c7652400\n"
- "cmpq rax,r11\n"
+ "movq tmp,0x000000098bca5a00\n"
+ "addq rax,tmp\n"
+ "movq tmp,0x00000009c7652400\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x3b9aca00\n"
"addl rax,0x3b9aca00\n"
"addl rax,0x3b9aca00\n"
"addl rax,0x3b9aca00\n"
- "movl r11,0xee6b2800\n"
- "cmpq rax,r11\n"
+ "movl tmp,0xee6b2800\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x3b9aca00\n"
"subl rax,0x4d2fa200\n"
"addl rax,0x3b9aca00\n"
"subl rax,0x3b9aca00\n"
- "movl r11,0xee6b2800\n"
- "cmpq rax,r11\n"
+ "movl tmp,0xee6b2800\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x3b9aca00\n"
- "movq r11,0x0000000a02ffee00\n"
- "subq rax,r11\n"
- "movq r11,0xfffffff6389adc00\n"
- "cmpq rax,r11\n"
+ "movq tmp,0x0000000a02ffee00\n"
+ "subq rax,tmp\n"
+ "movq tmp,0xfffffff6389adc00\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movq rax,-0x3b9aca00\n"
@@ -6058,8 +6058,8 @@
"subl rax,0x4d2fa200\n"
"subl rax,0x3b9aca00\n"
"addl rax,0x3b9aca00\n"
- "movl r11,0xee6b2800\n"
- "cmpq rax,r11\n"
+ "movl tmp,0xee6b2800\n"
+ "cmpq rax,tmp\n"
"jz +7\n"
"int3\n"
"movl rax,0x2a\n"
diff --git a/runtime/vm/compiler/ffi/native_location.cc b/runtime/vm/compiler/ffi/native_location.cc
index f757a31..7b362fd 100644
--- a/runtime/vm/compiler/ffi/native_location.cc
+++ b/runtime/vm/compiler/ffi/native_location.cc
@@ -277,14 +277,14 @@
void NativeRegistersLocation::PrintTo(BaseTextBuffer* f) const {
if (num_regs() == 1) {
- f->Printf("%s", RegisterNames::RegisterName(regs_->At(0)));
+ f->Printf("%s", RegisterNames::RegisterAbiName(regs_->At(0)));
} else {
f->AddString("(");
for (intptr_t i = 0; i < num_regs(); i++) {
if (i != 0) {
f->Printf(", ");
}
- f->Printf("%s", RegisterNames::RegisterName(regs_->At(i)));
+ f->Printf("%s", RegisterNames::RegisterAbiName(regs_->At(i)));
}
f->AddString(")");
}
diff --git a/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv32_linux.expect
index f5fde9e..5dcb075 100644
--- a/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv32_linux.expect
@@ -7,8 +7,8 @@
fa6 double
fa7 double
(a0, a1) int64[double]
-(a2, tmp) int64[double]
-(tmp2, pp) int64[double]
+(a2, a3) int64[double]
+(a4, a5) int64[double]
(a6, a7) int64[double]
S+0 double
S+8 double
diff --git a/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv64_linux.expect
index 810b278..a46f1fb 100644
--- a/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/doublex20/riscv64_linux.expect
@@ -9,9 +9,9 @@
a0 int64[double]
a1 int64[double]
a2 int64[double]
-tmp int64[double]
-tmp2 int64[double]
-pp int64[double]
+a3 int64[double]
+a4 int64[double]
+a5 int64[double]
a6 int64[double]
a7 int64[double]
S+0 double
diff --git a/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv32_linux.expect
index 663376f..edb61cc 100644
--- a/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv32_linux.expect
@@ -7,8 +7,8 @@
fa6 float
fa7 float
(a0, a1) int64[float]
-(a2, tmp) int64[float]
-(tmp2, pp) int64[float]
+(a2, a3) int64[float]
+(a4, a5) int64[float]
(a6, a7) int64[float]
S+0 float
S+4 float
diff --git a/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv64_linux.expect
index 4531dae..b8030e0 100644
--- a/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/floatx20/riscv64_linux.expect
@@ -9,9 +9,9 @@
a0 int64[float]
a1 int64[float]
a2 int64[float]
-tmp int64[float]
-tmp2 int64[float]
-pp int64[float]
+a3 int64[float]
+a4 int64[float]
+a5 int64[float]
a6 int64[float]
a7 int64[float]
S+0 float
diff --git a/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv32_linux.expect
index 84bc85d..71c8bd7 100644
--- a/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv32_linux.expect
@@ -1,9 +1,9 @@
a0 int32[int8]
a1 int32[int8]
a2 int32[int8]
-tmp int32[int8]
-tmp2 int32[int8]
-pp int32[int8]
+a3 int32[int8]
+a4 int32[int8]
+a5 int32[int8]
a6 int32[int8]
a7 int32[int8]
S+0 int8
diff --git a/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv64_linux.expect
index 84bc85d..71c8bd7 100644
--- a/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/int8x10/riscv64_linux.expect
@@ -1,9 +1,9 @@
a0 int32[int8]
a1 int32[int8]
a2 int32[int8]
-tmp int32[int8]
-tmp2 int32[int8]
-pp int32[int8]
+a3 int32[int8]
+a4 int32[int8]
+a5 int32[int8]
a6 int32[int8]
a7 int32[int8]
S+0 int8
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv32_linux.expect
index fda1302..2f0c36f 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv32_linux.expect
@@ -1,8 +1,8 @@
P(a0 uint32) Struct(size: 12)
P(a1 uint32) Struct(size: 12)
P(a2 uint32) Struct(size: 12)
-P(tmp uint32) Struct(size: 12)
-P(tmp2 uint32) Struct(size: 12)
-P(pp uint32) Struct(size: 12)
+P(a3 uint32) Struct(size: 12)
+P(a4 uint32) Struct(size: 12)
+P(a5 uint32) Struct(size: 12)
=>
(a0, a1) int64
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv64_linux.expect
index ad37cf7..c9dc492 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct12bytesFloatx6/riscv64_linux.expect
@@ -1,6 +1,6 @@
M(a0 int64, a1 int64) Struct(size: 12)
-M(a2 int64, tmp int64) Struct(size: 12)
-M(tmp2 int64, pp int64) Struct(size: 12)
+M(a2 int64, a3 int64) Struct(size: 12)
+M(a4 int64, a5 int64) Struct(size: 12)
M(a6 int64, a7 int64) Struct(size: 12)
M(S+0 int64, S+8 int64) Struct(size: 12)
M(S+16 int64, S+24 int64) Struct(size: 12)
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv32_linux.expect
index 664653c..4824868 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv32_linux.expect
@@ -1,9 +1,9 @@
P(a1 uint32) Struct(size: 16)
fa0 float
P(a2 uint32) Struct(size: 16)
-P(tmp uint32) Struct(size: 16)
-P(tmp2 uint32) Struct(size: 16)
-P(pp uint32) Struct(size: 16)
+P(a3 uint32) Struct(size: 16)
+P(a4 uint32) Struct(size: 16)
+P(a5 uint32) Struct(size: 16)
P(a6 uint32) Struct(size: 16)
P(a7 uint32) Struct(size: 16)
P(S+0 uint32) Struct(size: 16)
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv64_linux.expect
index 6f7ef5b..620273c 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct16bytesHomogenousx10/riscv64_linux.expect
@@ -1,7 +1,7 @@
M(a0 int64, a1 int64) Struct(size: 16)
fa0 float
-M(a2 int64, tmp int64) Struct(size: 16)
-M(tmp2 int64, pp int64) Struct(size: 16)
+M(a2 int64, a3 int64) Struct(size: 16)
+M(a4 int64, a5 int64) Struct(size: 16)
M(a6 int64, a7 int64) Struct(size: 16)
M(S+0 int64, S+8 int64) Struct(size: 16)
M(S+16 int64, S+24 int64) Struct(size: 16)
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv32_linux.expect
index d326d70..39e23b8c 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv32_linux.expect
@@ -1,9 +1,9 @@
M(a0 uint32) Struct(size: 3)
M(a1 uint32) Struct(size: 3)
M(a2 uint32) Struct(size: 3)
-M(tmp uint32) Struct(size: 3)
-M(tmp2 uint32) Struct(size: 3)
-M(pp uint32) Struct(size: 3)
+M(a3 uint32) Struct(size: 3)
+M(a4 uint32) Struct(size: 3)
+M(a5 uint32) Struct(size: 3)
M(a6 uint32) Struct(size: 3)
M(a7 uint32) Struct(size: 3)
M(S+0 uint32) Struct(size: 3)
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv64_linux.expect
index 3f71e45..b67660c 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct3bytesx10/riscv64_linux.expect
@@ -1,9 +1,9 @@
M(a0 int64) Struct(size: 3)
M(a1 int64) Struct(size: 3)
M(a2 int64) Struct(size: 3)
-M(tmp int64) Struct(size: 3)
-M(tmp2 int64) Struct(size: 3)
-M(pp int64) Struct(size: 3)
+M(a3 int64) Struct(size: 3)
+M(a4 int64) Struct(size: 3)
+M(a5 int64) Struct(size: 3)
M(a6 int64) Struct(size: 3)
M(a7 int64) Struct(size: 3)
M(S+0 int64) Struct(size: 3)
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv32_linux.expect
index 8c5778d..14ea892 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv32_linux.expect
@@ -1,6 +1,6 @@
M(a0 uint32, a1 uint32) Struct(size: 8)
-M(a2 uint32, tmp uint32) Struct(size: 8)
-M(tmp2 uint32, pp uint32) Struct(size: 8)
+M(a2 uint32, a3 uint32) Struct(size: 8)
+M(a4 uint32, a5 uint32) Struct(size: 8)
M(a6 uint32, a7 uint32) Struct(size: 8)
M(S+0 uint32, S+4 uint32) Struct(size: 8)
M(S+8 uint32, S+12 uint32) Struct(size: 8)
diff --git a/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv64_linux.expect
index 7bd998e..b0e7ecb 100644
--- a/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/struct8bytesPackedx10/riscv64_linux.expect
@@ -1,9 +1,9 @@
M(a0 int64) Struct(size: 8)
M(a1 int64) Struct(size: 8)
M(a2 int64) Struct(size: 8)
-M(tmp int64) Struct(size: 8)
-M(tmp2 int64) Struct(size: 8)
-M(pp int64) Struct(size: 8)
+M(a3 int64) Struct(size: 8)
+M(a4 int64) Struct(size: 8)
+M(a5 int64) Struct(size: 8)
M(a6 int64) Struct(size: 8)
M(a7 int64) Struct(size: 8)
M(S+0 int64) Struct(size: 8)
diff --git a/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv32_linux.expect
index da14e5c..d84073a5 100644
--- a/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv32_linux.expect
@@ -1,9 +1,9 @@
M(a0 int32[int8], fa0 double) Struct(size: 9)
M(a1 int32[int8], fa1 double) Struct(size: 9)
M(a2 int32[int8], fa2 double) Struct(size: 9)
-M(tmp int32[int8], fa3 double) Struct(size: 9)
-M(tmp2 int32[int8], fa4 double) Struct(size: 9)
-M(pp int32[int8], fa5 double) Struct(size: 9)
+M(a3 int32[int8], fa3 double) Struct(size: 9)
+M(a4 int32[int8], fa4 double) Struct(size: 9)
+M(a5 int32[int8], fa5 double) Struct(size: 9)
M(a6 int32[int8], fa6 double) Struct(size: 9)
M(a7 int32[int8], fa7 double) Struct(size: 9)
P(S+0 uint32) Struct(size: 9)
diff --git a/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv64_linux.expect
index d4389d5..eee3c90 100644
--- a/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/structPacked/riscv64_linux.expect
@@ -1,9 +1,9 @@
M(a0 int32[int8], fa0 double) Struct(size: 9)
M(a1 int32[int8], fa1 double) Struct(size: 9)
M(a2 int32[int8], fa2 double) Struct(size: 9)
-M(tmp int32[int8], fa3 double) Struct(size: 9)
-M(tmp2 int32[int8], fa4 double) Struct(size: 9)
-M(pp int32[int8], fa5 double) Struct(size: 9)
+M(a3 int32[int8], fa3 double) Struct(size: 9)
+M(a4 int32[int8], fa4 double) Struct(size: 9)
+M(a5 int32[int8], fa5 double) Struct(size: 9)
M(a6 int32[int8], fa6 double) Struct(size: 9)
M(a7 int32[int8], fa7 double) Struct(size: 9)
M(S+0 int64, S+8 int64) Struct(size: 9)
diff --git a/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv32_linux.expect
index 7a6a9ef..f60a8fe 100644
--- a/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv32_linux.expect
@@ -1,8 +1,8 @@
P(a1 uint32) Union(size: 16)
P(a2 uint32) Union(size: 16)
-P(tmp uint32) Union(size: 16)
-P(tmp2 uint32) Union(size: 16)
-P(pp uint32) Union(size: 16)
+P(a3 uint32) Union(size: 16)
+P(a4 uint32) Union(size: 16)
+P(a5 uint32) Union(size: 16)
P(a6 uint32) Union(size: 16)
P(a7 uint32) Union(size: 16)
P(S+0 uint32) Union(size: 16)
diff --git a/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv64_linux.expect
index 35d836b..94bc67b 100644
--- a/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/union16bytesHomogenousx10/riscv64_linux.expect
@@ -1,6 +1,6 @@
M(a0 int64, a1 int64) Union(size: 16)
-M(a2 int64, tmp int64) Union(size: 16)
-M(tmp2 int64, pp int64) Union(size: 16)
+M(a2 int64, a3 int64) Union(size: 16)
+M(a4 int64, a5 int64) Union(size: 16)
M(a6 int64, a7 int64) Union(size: 16)
M(S+0 int64, S+8 int64) Union(size: 16)
M(S+16 int64, S+24 int64) Union(size: 16)
diff --git a/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv32_linux.expect b/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv32_linux.expect
index 95a498c..9ac54e5 100644
--- a/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv32_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv32_linux.expect
@@ -1,6 +1,6 @@
M(a0 uint32, a1 uint32) Union(size: 5)
-M(a2 uint32, tmp uint32) Union(size: 5)
-M(tmp2 uint32, pp uint32) Union(size: 5)
+M(a2 uint32, a3 uint32) Union(size: 5)
+M(a4 uint32, a5 uint32) Union(size: 5)
M(a6 uint32, a7 uint32) Union(size: 5)
M(S+0 uint32, S+4 uint32) Union(size: 5)
M(S+8 uint32, S+12 uint32) Union(size: 5)
diff --git a/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv64_linux.expect b/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv64_linux.expect
index 9165726..6116be3 100644
--- a/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv64_linux.expect
+++ b/runtime/vm/compiler/ffi/unit_tests/union5bytesPackedx10/riscv64_linux.expect
@@ -1,9 +1,9 @@
M(a0 int64) Union(size: 5)
M(a1 int64) Union(size: 5)
M(a2 int64) Union(size: 5)
-M(tmp int64) Union(size: 5)
-M(tmp2 int64) Union(size: 5)
-M(pp int64) Union(size: 5)
+M(a3 int64) Union(size: 5)
+M(a4 int64) Union(size: 5)
+M(a5 int64) Union(size: 5)
M(a6 int64) Union(size: 5)
M(a7 int64) Union(size: 5)
M(S+0 int64) Union(size: 5)
diff --git a/runtime/vm/constants.h b/runtime/vm/constants.h
index 26514bf..b56c7e1 100644
--- a/runtime/vm/constants.h
+++ b/runtime/vm/constants.h
@@ -41,6 +41,10 @@
ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
return cpu_reg_names[reg];
}
+ static const char* RegisterAbiName(Register reg) {
+ ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
+ return cpu_reg_abi_names[reg];
+ }
static const char* FpuRegisterName(FpuRegister reg) {
ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
return fpu_reg_names[reg];
diff --git a/runtime/vm/constants_arm.cc b/runtime/vm/constants_arm.cc
index 03e790f..b0e289a 100644
--- a/runtime/vm/constants_arm.cc
+++ b/runtime/vm/constants_arm.cc
@@ -14,11 +14,21 @@
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
#if defined(DART_TARGET_OS_MACOS) || defined(DART_TARGET_OS_MACOS_IOS)
- "r0", "r1", "r2", "r3", "r4", "pp", "r6", "fp",
- "r8", "r9", "thr", "r11", "ip", "sp", "lr", "pc",
+ "r0", "r1", "r2", "r3", "r4", "pp", "r6", "fp",
+ "r8", "r9", "thr", "r11", "tmp", "sp", "lr", "pc",
#else
- "r0", "r1", "r2", "r3", "r4", "pp", "r6", "r7",
- "r8", "r9", "thr", "fp", "ip", "sp", "lr", "pc",
+ "r0", "r1", "r2", "r3", "r4", "pp", "r6", "r7",
+ "r8", "r9", "thr", "fp", "tmp", "sp", "lr", "pc",
+#endif
+};
+
+const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
+#if defined(DART_TARGET_OS_MACOS) || defined(DART_TARGET_OS_MACOS_IOS)
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "fp",
+ "r8", "r9", "r10", "r11", "ip", "sp", "lr", "pc",
+#else
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
#endif
};
diff --git a/runtime/vm/constants_arm.h b/runtime/vm/constants_arm.h
index b7f2374..d560e44 100644
--- a/runtime/vm/constants_arm.h
+++ b/runtime/vm/constants_arm.h
@@ -294,6 +294,7 @@
const FpuRegister kNoFpuRegister = kNoQRegister;
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
+extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
extern const char* const fpu_reg_names[kNumberOfFpuRegisters];
extern const char* const fpu_s_reg_names[kNumberOfSRegisters];
extern const char* const fpu_d_reg_names[kNumberOfDRegisters];
diff --git a/runtime/vm/constants_arm64.cc b/runtime/vm/constants_arm64.cc
index c10999b..111e74e 100644
--- a/runtime/vm/constants_arm64.cc
+++ b/runtime/vm/constants_arm64.cc
@@ -11,9 +11,16 @@
namespace dart {
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "sp",
+ "tmp", "tmp2", "r18", "r19", "r20", "r21", "nr", "r23",
+ "r24", "r25", "thr", "pp", "mask", "fp", "lr", "csp",
+};
+
+const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
- "r11", "r12", "r13", "r14", "r15", "ip0", "ip1", "r18", "r19", "r20", "r21",
- "nr", "r23", "r24", "r25", "r26", "pp", "r28", "fp", "lr", "r31",
+ "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
+ "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "sp",
};
const char* const fpu_reg_names[kNumberOfFpuRegisters] = {
diff --git a/runtime/vm/constants_arm64.h b/runtime/vm/constants_arm64.h
index b2f4e6e..9b4df71 100644
--- a/runtime/vm/constants_arm64.h
+++ b/runtime/vm/constants_arm64.h
@@ -129,6 +129,7 @@
const FpuRegister kNoFpuRegister = kNoVRegister;
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
+extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
extern const char* const fpu_reg_names[kNumberOfFpuRegisters];
// Register aliases.
diff --git a/runtime/vm/constants_ia32.cc b/runtime/vm/constants_ia32.cc
index bbe4feb..057264d 100644
--- a/runtime/vm/constants_ia32.cc
+++ b/runtime/vm/constants_ia32.cc
@@ -13,6 +13,9 @@
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
+const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
+ "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
+
const char* const fpu_reg_names[kNumberOfXmmRegisters] = {
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"};
diff --git a/runtime/vm/constants_ia32.h b/runtime/vm/constants_ia32.h
index d06f97f..061771d 100644
--- a/runtime/vm/constants_ia32.h
+++ b/runtime/vm/constants_ia32.h
@@ -67,6 +67,7 @@
const FpuRegister kNoFpuRegister = kNoXmmRegister;
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
+extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
extern const char* const fpu_reg_names[kNumberOfXmmRegisters];
// Register aliases.
diff --git a/runtime/vm/constants_riscv.cc b/runtime/vm/constants_riscv.cc
index 6f694e9..7c9b6ed 100644
--- a/runtime/vm/constants_riscv.cc
+++ b/runtime/vm/constants_riscv.cc
@@ -23,6 +23,12 @@
"s6", "s7", "s8", "s9", "null", "mask", "t3", "t4", "t5", "t6",
};
+const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
+ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0",
+ "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5",
+ "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
+};
+
const char* const fpu_reg_names[kNumberOfFpuRegisters] = {
"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
diff --git a/runtime/vm/constants_riscv.h b/runtime/vm/constants_riscv.h
index a03694c..645b69e 100644
--- a/runtime/vm/constants_riscv.h
+++ b/runtime/vm/constants_riscv.h
@@ -143,6 +143,7 @@
typedef double fpu_register_t;
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
+extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
extern const char* const fpu_reg_names[kNumberOfFpuRegisters];
// Register aliases.
diff --git a/runtime/vm/constants_x64.cc b/runtime/vm/constants_x64.cc
index b80a77a..7e03cb6 100644
--- a/runtime/vm/constants_x64.cc
+++ b/runtime/vm/constants_x64.cc
@@ -12,7 +12,11 @@
const char* const cpu_reg_names[kNumberOfCpuRegisters] = {
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
- "r8", "r9", "r10", "r11", "r12", "r13", "thr", "pp"};
+ "r8", "r9", "r10", "tmp", "r12", "r13", "thr", "pp"};
+
+const char* const cpu_reg_abi_names[kNumberOfCpuRegisters] = {
+ "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
const char* const fpu_reg_names[kNumberOfXmmRegisters] = {
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
diff --git a/runtime/vm/constants_x64.h b/runtime/vm/constants_x64.h
index aae0a4c..a880647 100644
--- a/runtime/vm/constants_x64.h
+++ b/runtime/vm/constants_x64.h
@@ -99,6 +99,7 @@
const FpuRegister kNoFpuRegister = kNoXmmRegister;
extern const char* const cpu_reg_names[kNumberOfCpuRegisters];
+extern const char* const cpu_reg_abi_names[kNumberOfCpuRegisters];
extern const char* const fpu_reg_names[kNumberOfXmmRegisters];
enum RexBits {
