diff --git a/runtime/vm/compiler/assembler/assembler_arm64.h b/runtime/vm/compiler/assembler/assembler_arm64.h
index 21149ef..79eff28 100644
--- a/runtime/vm/compiler/assembler/assembler_arm64.h
+++ b/runtime/vm/compiler/assembler/assembler_arm64.h
@@ -881,6 +881,9 @@
   void clz(Register rd, Register rn) {
     EmitMiscDP1Source(CLZ, rd, rn, kEightBytes);
   }
+  void clzw(Register rd, Register rn) {
+    EmitMiscDP1Source(CLZ, rd, rn, kFourBytes);
+  }
 
   // Reverse bits.
   void rbit(Register rd, Register rn) {
diff --git a/runtime/vm/compiler/assembler/assembler_arm64_test.cc b/runtime/vm/compiler/assembler/assembler_arm64_test.cc
index f4b0afb..62129c2 100644
--- a/runtime/vm/compiler/assembler/assembler_arm64_test.cc
+++ b/runtime/vm/compiler/assembler/assembler_arm64_test.cc
@@ -1279,6 +1279,44 @@
   EXPECT_EQ(0, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
 }
 
+ASSEMBLER_TEST_GENERATE(Clzw, assembler) {
+  Label error;
+
+  __ clzw(R1, ZR);
+  __ cmp(R1, Operand(32));
+  __ b(&error, NE);
+  __ LoadImmediate(R2, 42);
+  __ clzw(R2, R2);
+  __ cmp(R2, Operand(26));
+  __ b(&error, NE);
+  __ LoadImmediate(R0, -1);
+  __ clzw(R1, R0);
+  __ cmp(R1, Operand(0));
+  __ b(&error, NE);
+  __ add(R0, ZR, Operand(R0, LSR, 35));
+  __ clzw(R1, R0);
+  __ cmp(R1, Operand(3));
+  __ b(&error, NE);
+  __ LoadImmediate(R0, 0xFFFFFFFF0FFFFFFF);
+  __ clzw(R1, R0);
+  __ cmp(R1, Operand(4));
+  __ b(&error, NE);
+  __ LoadImmediate(R0, 0xFFFFFFFF);
+  __ clzw(R1, R0);
+  __ cmp(R1, Operand(0));
+  __ b(&error, NE);
+  __ mov(R0, ZR);
+  __ ret();
+  __ Bind(&error);
+  __ LoadImmediate(R0, 1);
+  __ ret();
+}
+
+ASSEMBLER_TEST_RUN(Clzw, test) {
+  typedef int64_t (*Int64Return)() DART_UNUSED;
+  EXPECT_EQ(0, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
+}
+
 ASSEMBLER_TEST_GENERATE(Rbit, assembler) {
   const int64_t immediate = 0x0000000000000015;
   __ LoadImmediate(R0, immediate);
diff --git a/runtime/vm/simulator_arm64.cc b/runtime/vm/simulator_arm64.cc
index 63d9e07..11cf428 100644
--- a/runtime/vm/simulator_arm64.cc
+++ b/runtime/vm/simulator_arm64.cc
@@ -2573,19 +2573,11 @@
   switch (op) {
     case 4: {
       // Format(instr, "clz'sf 'rd, 'rn");
-      int64_t rd_val = 0;
-      int64_t rn_val = (instr->SFField() == 1) ? rn_val64 : rn_val32;
-      if (rn_val != 0) {
-        while (rn_val > 0) {
-          rd_val++;
-          rn_val <<= 1;
-        }
-      } else {
-        rd_val = (instr->SFField() == 1) ? 64 : 32;
-      }
       if (instr->SFField() == 1) {
+        const uint64_t rd_val = Utils::CountLeadingZeros64(rn_val64);
         set_register(instr, rd, rd_val, R31IsZR);
       } else {
+        const uint32_t rd_val = Utils::CountLeadingZeros32(rn_val32);
         set_wregister(rd, rd_val, R31IsZR);
       }
       break;
diff --git a/tools/VERSION b/tools/VERSION
index 836aaa1..d068d72 100644
--- a/tools/VERSION
+++ b/tools/VERSION
@@ -27,5 +27,5 @@
 MAJOR 2
 MINOR 13
 PATCH 0
-PRERELEASE 74
+PRERELEASE 75
 PRERELEASE_PATCH 0
\ No newline at end of file